The present invention relates to power semiconductor devices, and more particularly to power MOSFETs formed in silicon carbide (SiC).
Power MOSFETs are well known for their ability to carry large currents in the on-state while withstanding large breakdown voltages in the off-state. In such a device, current flow between source and drain regions in a semiconductor substrate is controlled by a voltage applied to a gate electrode that is separated from the semiconductor surface by an insulator, typically silicon dioxide. In an n-type enhancement MOSFET, for example, a positive bias on the gate causes a surface inversion layer—or channel—to form in a p-type region under the gate oxide and thereby creates a conductive path between source and drain. The application of a positive drain voltage then produces current flow between drain and source. Lateral and vertical power MOSFET structures in silicon have been explored over the years, the former type having the drain, gate and source terminals on the same surface of the silicon wafer, the latter type having the source and drain on opposite surfaces of the wafer. Several different types of vertical power MOSFETs have been proposed, including the double-diffused MOSFET (DMOSFET) and the UMOSFET. These and other power MOSFETs are described in a textbook by B. Jayant Baliga entitled Power Semiconductor Devices, PWS Publishing Co. (1996), the disclosure of which is hereby incorporated herein by reference.
Although silicon has been the material of choice for many semiconductor applications, its fundamental electronic structure and characteristics prevent its utilization beyond certain parameters. Thus, interest in power MOSFET devices has turned from silicon to other materials, including silicon carbide. SiC power switching devices have significant advantages over silicon devices, including faster switching speed, lower specific on-resistance and thus lower power losses. SiC has a breakdown electric field that is an order of magnitude higher than that of silicon, which allows for a thinner drift region and thus a lower drift region resistance. The resistance of the drift region is proportional to the region's thickness and inversely proportional to the doping. With decreases in thickness and increases in doping of the drift region, the specific on-resistance of a SiC device can be 100-200 times lower than that of a comparable silicon device of equal voltage rating.
The DMOS and UMOS structures remain of interest for SiC MOSFETs, although in this context the term “DMOSFET” is used to refer to a “double-implanted” MOSFET, in which the base and source regions are produced by ion implantation rather than thermal diffusion because diffusion is impractical in SiC due to very low diffusion coefficients in the material. Examples of such devices are described in U.S. Pat. No. 5,506,421 to Palmour, U.S. Pat. No. 6,180,958 to Cooper, and U.S. Pat. No. 6,238,980 to Ueno, all of which patents are incorporated by reference.
In spite of substantial activity in this area, the potential advantages of SiC for power MOSFETs have not been fully realized. There is a continuing need for improvements, including reductions in specific on-resistance without undesirable side-effects, and more reliable or otherwise improved methods of fabrication.